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high speed, triple differential receiver with comparators ad8145 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2010 analog devices, inc. all rights reserved. features high speed: 500 mhz, 2000 v/s @ g = 1, v out = 2 v p-p 0.1 db flatness out to 75 mhz high cmrr: 69 db @ 10 mhz high differential input impedance: 1 m wide input common-mode range: 3.5 v (5 v supplies) on-chip, gain setting resistors can be configured for gain of 1 or 2 fast settling: 15 ns to 0.1% @ 2 v p-p low input referred noise: 13 nv/hz disable feature small packaging: 32-lead, 5 mm 5 mm lfcsp aec-q10 qualified (ad8145w) applications rgb video receivers ypbpr video receivers keyboard, video, mouse (kvm) unshielded twisted pair (utp) receivers automotive driver assistance (ad8145w) automotive infotainment (ad8145w) functional block diagram out_g out_b out_r compb_in+ compb_in? gnd gnd 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 2526 27 2829303132 v s+ gnd v s? dis/pd ref_b gain_b in+_b in?_b gnd gnd ref_g g ain_g in+_g in?_g ref_r gain_r gnd gnd compb_out compa_out compa_in? compa_in+ in?_r in+_r gnd 9 10111213141516 + ? + ? + ? + ? c rr a b + ? + ? c c rr r r ad8145 0 6307-001 figure 1. general description the ad8145 is a triple, low cost, differential-to-single-ended receiver specifically designed for receiving red-green-blue (rgb) video signals over twisted pair cable or differential printed circuit board (pcb) traces. it can also be used to receive any type of analog signal or high speed data transmission. two auxiliary comparators with hysteresis are provided that can be used to decode video sync signals, which are encoded on the received common-mode voltages, to receive digital signals or as general- purpose comparators. the ad8145 can be used in conjunction with the ad8133 or ad8134 triple differential drivers to provide a complete low cost solution for rgb over category 5 utp cable applications, including kvm. the excellent common-mode rejection (69 db @ 10 mhz) of the ad8145 allows for the use of low cost, unshielded twisted pair cables in noisy environments. the ad8145 can be configured for a differential-to-single-ended gain of 1 or 2 by connecting the gain_x pin of each channel to its respective output (g = 1) or connecting it to a reference voltage (g = 2), which is normally grounded. a ref_x input is provided on each channel that allows designers to level shift the output signals. the ad8145w is the automotive grade version that is qualified per the aec-q100 for use in automotive applications. see the automotive products section for more details. the ad8145 is available in a 5 mm 5 mm, 32-lead lfcsp and is rated to work over the extended industrial temperature range of ?40c to +105c.
ad8145 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? maximum power dissipation ..................................................... 7 ? esd caution .................................................................................. 7 ? pin configuration and function description .............................. 8 ? typical performance characteristics ............................................. 9 ? theory of operation ...................................................................... 14 ? applications information .............................................................. 15 ? overview ..................................................................................... 15 ? basic closed-loop gain configurations ................................ 15 ? terminating the input................................................................ 16 ? input clamping ........................................................................... 17 ? pcb layout considerations ...................................................... 18 ? driving a capacitive load ......................................................... 19 ? power-down ............................................................................... 19 ? automotive products ................................................................. 19 ? comparators ............................................................................... 19 ? sync pulse extraction using comparators ............................. 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history 1/10rev. 0 to rev. a changes to features section, applications section, and general description section .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 added automotive products section .......................................... 19 added exposed paddle notation to outline dimensions ........ 21 changes to ordering guide .......................................................... 21 10/06revision 0: initial version
ad8145 rev. a | page 3 of 24 specifications t a = 25c, v s = 5 v, ref_x = 0 v, r l = 150 , c l = 2 pf, g = 1, t min to t max = ?40c to +105c, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 0.2 v p-p 530 mhz v out = 2 v p-p 500 mhz v out = 0.2 v p-p, g = 2 200 mhz v out = 2 v p-p, g = 2 200 mhz bandwidth for 0.1 db flatness v out = 2 v p-p 75 mhz v out = 2 v p-p, g = 2 100 mhz slew rate v out = 2 v p-p 2100 v/s v out = 2 v p-p, g = 2 2100 v/s settling time v out = 2 v p-p, 0.1% 15 ns output overdrive recovery 20 ns noise/distortion second harmonic v out = 2 v p-p, 1 mhz ?67 dbc third harmonic v out = 2 v p-p, 1 mhz ?88 dbc crosstalk v out = 2 v p-p, 10 mhz ?62 db input voltage noise (rti) f 10 khz 13 nv/hz differential gain error ntsc, 200 ire, r l 150 0.25 % differential phase error ntsc, 200 ire, r l 150 0.1 degrees input characteristics common-mode rejection dc, v cm = ?2 v to +2 v 81 90 db ad8145w only, t min to t max 78 db v cm = 1 v p-p, f = 10 mhz 69 db v cm = 1 v p-p, f = 100 mhz 41 db common-mode voltage range v +in ? v ?in = 0 v 3.5 v differential operating range 2.5 v resistance differential 1 m common mode 1.3 m capacitance differential 1 pf common mode 2 pf dc performance closed-loop gain dc, g = 2 1.955 1.985 2.020 v/v ad8145w only, t min to t max 1.930 2.030 v/v output offset voltage g = 2 ?17.5 +7.0 +1.0 mv ad8145w only, t min to t max ?25 +8.0 mv output offset voltage drift t min to t max ?18 v/c input bias current (+in, ?in) ?6 ?3.4 ?0.9 a ad8145w only, t min to t max ?7 ?0.5 a input bias current drift t min to t max (+in, ?in) 25 na/c input offset current ?400 ?65 +300 na ad8145w only, t min to t max ?650 +650 na output performance voltage swing ?3.64 +3.55 v ad8145w only, t min to t max ?3.45 +3.35 v output current 50 ma short-circuit current short to gnd, source/sink +195/?230 ma
ad8145 rev. a | page 4 of 24 parameter conditions min typ max unit comparator performance v oh r l = 1 k 3.205 3.310 v ad8145w only, t min to t max 2.950 v v ol r l = 1 k 0.390 0.420 v ad8145w only, t min to t max 0.440 v input offset voltage 2.5 mv hysteresis width 18 mv input bias current 1.5 a propagation delay, t plh 6 ns propagation delay, t phl 6 ns rise time 10% to 90% 6 ns fall time 10% to 90% 2 ns power-down performance power-down v ih v s+ ? 1.65 v power-down v il v s+ ? 2.65 v power-down i ih 0.5 a power-down i il ?250 a power-down assert time 1 s power supply operating range 4.5 11 v quiescent current, positive supply 48.5 57.5 ma ad8145w only, t min to t max 70 ma disabled 16 19.5 ma ad8145w only, t min to t max 25 ma quiescent current, negative supply ?52 ?43.5 ma ad8145w only, t min to t max ?65 ma disabled ?13.9 ?11 ma ad8145w only, t min to t max ?20 ma psrr, positive supply dc ?79 ?70 db ad8145w only, t min to t max ?66 db psrr, negative supply dc ?68 ?57 db ad8145w only, t min to t max ?54 db
ad8145 rev. a | page 5 of 24 t a = 25c, v s = 2.5 v, ref_x = 0 v, r l = 1 k, c l = 2 pf, g = 1, t min to t max = ?40c to +105c, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 0.2 v p-p 450 mhz v out = 2 v p-p 425 mhz v out = 0.2 v p-p, g = 2, r l = 150 180 mhz v out = 2 v p-p, g = 2, r l = 150 180 mhz bandwidth for 0.1 db flatness v out = 2 v p-p 53 mhz v out = 2 v p-p, g = 2, r l = 150 100 mhz slew rate v out = 2 v p-p 2000 v/s v out = 2 v p-p, g = 2, r l = 150 2000 v/s settling time v out = 2 v p-p, 0.1% 16 ns output overdrive recovery 10 ns noise/distortion second harmonic v out = 1 v p-p, 1 mhz ?71 dbc third harmonic v out = 1 v p-p, 1 mhz ?76 dbc crosstalk v out = 1 v p-p, 10 mhz ?62 db input voltage noise (rti) f 10 khz 13 nv/hz input characteristics common-mode rejection dc, v cm = ?1 v to +1 v 78 86 db ad8145w only, t min to t max 75 db v cm = 1 v p-p, f = 10 mhz 72 db v cm = 1 v p-p, f = 100 mhz 43 db common-mode voltage range v +in ? v ?in = 0 v 1.25 v differential operating range 1.6 v resistance differential 1 m common mode 1.3 m capacitance differential 1 pf common mode 2 pf dc performance closed-loop gain dc, g = 2 1.960 1.985 2.016 v/v ad8145w only, t min to t max 1.930 2.030 v/v output offset voltage g = 2 ?13.5 ?4.5 +2 mv ad8145w only, t min to t max ?18 +8 mv output offset voltage drift t min to t max ?18 v/c input bias current (+in, ?in) ?6 ?3.5 ?0.9 a ad8145w only, t min to t max ?7 ?0.5 a input bias current drift t min to t max (+in, ?in) 25 na/c input offset current ?400 ?60 +300 na ad8145w only, t min to t max ?650 +650 na output performance voltage swing r l = 150 ?1.35 +1.3 v ad8145w only, t min to t max ?1.20 +1.15 v output current 25 ma short-circuit current short to gnd, source/sink +100/?100 ma power-down performance power-down v ih v s+ ? 1.5 v power-down v il v s+ ? 2.5 v power-down i ih 0.25 a power-down i il 50 a power-down assert time 1 s
ad8145 rev. a | page 6 of 24 parameter conditions min typ max unit power supply operating range 4.5 11 v quiescent current, positive supply 40 47 ma ad8145w only, t min to t max 57 ma disabled 13.5 16 ma ad8145w only, t min to t max 21 ma quiescent current, negative supply ?43.5 ?36 ma ad8145w only, t min to t max ?54 ma disabled ?12.5 ?10 ma ad8145w only, t min to t max ?17 ma psrr, positive supply dc ?83 ?73 db ad8145w only, t min to t max ?68 db psrr, negative supply dc ?67 ?62 db ad8145w only, t min to t max ?59 db
ad8145 rev. a | page 7 of 24 absolute maximum ratings maximum power dissipation table 3. parameter rating supply voltage 12 v power dissipation see figure 2 storage temperature range ?65c to +125c operating temperature range ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150c the maximum safe power dissipation in the ad8145 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8145. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends on the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. the power dissipated due to all of the loads is equal to the sum of the power dissipation due to each individual load. rms voltages and currents must be used in these calculations. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the pcb surface, which is thermally connected to a copper plane. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface, which is thermally connected to a copper plane to achieve the specified ja . table 4. thermal resistance package type ja jc unit 5 mm 5 mm, 32-lead lfcsp 47 8.5 c/w 4.5 0 ?40 ?20 0 20 40 60 80 100 ambient temperature (c) maximum power dissipation (w) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 06307-002 figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 32-lead lfcsp (47c/w) on a jedec standard 4-layer board with the underside paddle soldered to a pad, which is thermally connected to a pcb plane. esd caution figure 2. maximum power dissipation vs. temperature for a 4-layer board
ad8145 rev. a | page 8 of 24 pin configuration and function description pin 1 indicator 1 gnd 2 ref_g 3 g ain_g 4 in+_g 5 in?_g 6 ref_r 7 gain_r 8 gnd 24 gnd 23 out_b 22 out_g 21 out_r 20 v s+ 19 compb_in+ 18 compb_in? 17 gnd 9 g nd 10 in+_r 11 in?_r 12 compa_in+ 13 compa_in? 14 compa_o ut 15 compb_out 16 gnd 32 gnd 31 in?_b 30 in+_b 29 gain _b 28 ref_b 27 dis/pd 26 v s? 25 gnd ad8145 top view (not to scale) notes 1. exposed pad on underside of device must be connected to ground. 06307-003 figure 3. pin configuration table 5. pin function descriptions pin o. nemonic description 1, 8, 9, 16, 17, 24, 25, 32 gnd signal ground and thermal plane connection. (see the absolute maximum ratings section.) 2 ref_g reference input, green channel. 3 gain_g gain connection, green channel. 4 in+_g noninverting input, green channel. 5 in?_g inverting input, green channel. 6 ref_r reference input, red channel. 7 gain_r gain connection, red channel. 10 in+_r noninverting input, red channel. 11 in?_r inverting input, red channel. 12 compa_in+ positive input, comparator a. 13 compa_in? negative input, comparator a. 14 compa_out output, comparator a. 15 compb_out output, comparator b. 18 compb_in? negative input, comparator b. 19 compb_in+ positive input, comparator b. 20 v s+ positive power supply. 21 out_r output, red channel. 22 out_g output, green channel. 23 out_b output, blue channel. 26 v s? negative power supply. 27 dis/pd disable/power down. 28 ref_b reference input, blue channel. 29 gain_b gain connection, blue channel. 30 in+_b noninverting input, blue channel. 31 in?_b inverting input, blue channel. exposed underside pad gnd signal gr ound and thermal plane connection.
ad8145 rev. a | page 9 of 24 typical performance characteristics unless otherwise noted, g = 1, r l = 150 , c l = 2 pf, ref_x = midsupply, v s = 5 v, t a = 25c. refer to the circuit in figure 35 . 3 ?7 1 1000 frequency (mhz) gain (db) 10 100 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 +5v v out = 0.2v p-p 5v 06307-004 3 ?7 1 1000 frequency (mhz) gain (db) 10 100 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 5v +5v v out = 2v p-p 06307-007 figure 4. small signal frequency response at various power supplies, g = 1 figure 7. large signal frequency response at various power supplies, g = 1 9 ?1 1 1000 frequency (mhz) gain (db) 10 100 8 7 6 5 4 3 2 1 0 +5v 5v v out = 0.2v p-p 06307-005 9 ?1 1 1000 frequency (mhz) gain (db) 10 100 8 7 6 5 4 3 2 1 0 +5v v out = 2v p-p 5v 06307-008 figure 5. small signal frequency response at various power supplies, g = 2 figure 8. large signal frequency response at various power supplies, g = 2 3 ?7 1 1000 frequency (mhz) gain (db) 10 100 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v out = 2v p-p g = 2, c l = 10 + 2pf, r snub = 20 ? g = 2, c l = 0 + 2pf, r snub = 0 ? g = 1, c l = 10 + 2pf, r snub = 20 ? g = 1, c l = 0 + 2pf, r snub = 0 ? 06307-009 3 ?7 1 1000 frequency (mhz) gain (db) 10 100 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v out = 0.2v p-p g = 2, c l = 10 + 2pf, r snub = 20 ? g = 2, c l = 0 + 2pf, r snub = 0 ? g = 1, c l = 10 + 2pf, r snub = 20 ? g = 1, c l = 0 + 2pf, r snub = 0 ? 06307-006 figure 6. small signal frequency response at various gains and 10 pf capacitive load buffered by 20 resistor figure 9. large signal frequency response at various gains and 10 pf capacitive load buffered by 20 resistor
ad8145 rev. a | page 10 of 24 3 ?7 1 1000 frequency (mhz) gain (db) 10 100 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 v out = 0.2v p-p g = 2 g = 1 06307-010 figure 10. small signal frequency response at various gains 0.5 ?0.5 1 1000 frequency (mhz) gain (db) 10 100 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 v out = 2v p-p g = 2, v s = +5v g = 2, v s = 5v g = 1, v s = 5v g = 1, v s = +5v 06307-011 figure 11. 0.1 db flatness for various power supplies and gains 110 10 0.1 1000 frequency (mhz) common-mode rejection (db) 1 10 100 100 90 80 70 60 50 40 30 20 v s = +5v v s = 5v 06307-012 figure 12. common-mode rejection vs . frequency at various supplies 3 ?7 1 1000 frequency (mhz) gain (db) 10 100 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 g = 2 g = 1 v out = 2v p-p 06307-013 figure 13. large signal frequency response at various gains 1000 10 0.01 100000 frequency (khz) input voltage noise (nv/ hz) 0.1 1 10 100 1000 10000 100 06307-046 figure 14. input referred voltage noise vs. frequency 4 ?4 ?5 5 differential input voltage (v) output voltage (v) 3 2 1 0 ?1 ?2 ?3 ?4?3?2?101234 r l = open circuit g = 1 v s = 5v 06307-047 figure 15. differential input operating range
ad8145 rev. a | page 11 of 24 150 ?150 0 100 time (ns) voltage (mv) 100 50 0 ?50 ?100 10 20 30 40 50 60 70 80 90 v out = 0.2v p-p black = +5v gray = 5v 06307-016 figure 16. small signal transient response at various power supplies, g = 1 150 ?150 0 100 time (ns) voltage (mv) 100 50 0 ?50 ?100 10 20 30 40 50 60 70 80 90 black = +5v gray = 5v v out = 0.2v p-p 06307-017 figure 17. small signal transient response at various power supplies, g = 2 150 ?150 0 100 time (ns) voltage (mv) 100 50 0 ?50 ?100 10 20 30 40 50 60 70 80 90 v out = 0.2v p-p g = 2, c l = 0 + 2pf, r snub = 0 ? g = 2, c l = 10 + 2pf, r snub = 20 ? g = 1, c l = 0 + 2pf, r snub = 0 ? g = 1, c l = 10 + 2pf, r snub = 20 ? 06307-018 figure 18. small signal transient response at various gains and 10 pf capacitive load buffered by 20 resistor 1.5 ?1.5 0 100 time (ns) voltage (v) 1.0 0.5 0 ?0.5 ?1.0 10 20 30 40 50 60 70 80 90 black = +5v gray = 5v v out = 2v p-p 06307-019 figure 19. large signal transient response at various power supplies, g = 1 1.5 ?1.5 0 100 time (ns) voltage (v) 1.0 0.5 0 ?0.5 ?1.0 10 20 30 40 50 60 70 80 90 black = +5v gray = 5v v out = 2v p-p 06307-020 figure 20. large signal transient response at various power supplies, g = 2 1.5 ?1.5 0 100 time (ns) voltage (v) 1.0 0.5 0 ?0.5 ?1.0 10 20 30 40 50 60 70 80 90 v out = 2v p-p g = 1, c l = 0 + 2pf, r snub = 0 ? g = 1, c l = 10 + 2pf, r snub = 20 ? g = 2, c l = 0 + 2pf, r snub = 0 ? g = 2, c l = 10 + 2pf, r snub = 20 ? 06307-021 figure 21. large signal transient response at various gains and 10 pf capacitive load buffered by 20 resistor
ad8145 rev. a | page 12 of 24 2.0 ?2.0 05 time (ns) voltage (v) error (%) 0 1.6 1.2 0.8 0.4 0 ?0.4 ?0.8 ?1.2 ?1.6 0.5 ?0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 5 1015202530354045 error output input 06307-048 figure 22. settling time ? 50 ?80 0.1 100 frequency (mhz) distortion (dbc) 11 0 ?55 ?60 ?65 ?70 ?75 v s = 5v v s = +5v v out = 2v p-p 06307-023 figure 23. second harmonic distortion vs. frequency and power supplies, v out = 2 v p-p, g = 1 ? 50 ?80 0.1 100 frequency (mhz) distortion (dbc) 11 0 ?55 ?60 ?65 ?70 ?75 v out = 2v p-p v s = +5v v s = 5v 06307-024 figure 24. second harmonic distortion vs. frequency and power supplies, v out = 2 v p-p, g = 2 4500 0 05 output voltage (v p-p) slew rate (v/s) . 0 4000 3500 3000 2500 2000 1500 1000 500 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 negative slew rate positive slew rate 06307-049 figure 25. slew rate vs. output voltage swing ? 50 ?120 0.1 100 frequency (mhz) distortion (dbc) 11 0 v out = 2v p-p ?60 ?70 ?80 ?90 ?100 ?110 v s = +5v v s = 5v 06307-026 figure 26. third harmonic distortion vs. frequency and power supplies, v out = 2 v p-p, g = 1 ? 50 ?120 0.1 100 frequency (mhz) distortion (dbc) 11 0 v out = 2v p-p ?60 ?70 ?80 ?90 ?100 ?110 v s = +5v v s = 5v 06307-027 figure 27. third harmonic distortion vs. frequency and power supplies, v out = 2 v p-p, g = 2
ad8145 rev. a | page 13 of 24 65 15 ?60 120 temperature (c) supply current (ma) 60 55 50 45 40 35 30 25 20 ?40 ?20 0 20 40 60 80 100 r l = open circuit i cc (5v) i ee (2.5v) i ee (5v) i cc (2.5v) 06307-050 5 ?5 05 time (ns) voltage (v) 0 0 4 3 2 1 0 ?1 ?2 ?3 ?4 50 100 150 200 250 300 350 400 450 g = 2 +5v output +5v 2 v in 5v output 5v 2 v in 06307-030 figure 28. power supply current vs. temperature figure 31. output overdrive recovery 10 ?90 0.01 1000 frequency (mhz) psrr (db) 0.1 1 10 100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 black = 2.5v gray = 5v 06307-032 10 ?90 0.01 1000 frequency (mhz) psrr (db) 0.1 1 10 100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 black = +5v gray = 5v 06307-029 figure 32. negative power supply rejection ratio (psrr) vs. frequency figure 29. positive power supply rejection ratio (psrr) vs. frequency 3.5 0 ?15 15 v in (mv) v out (v) 3.0 2.5 2.0 1.5 1.0 0.5 ?10 ?5 0 5 10 06307-051 figure 30. comparator hysteresis
ad8145 rev. a | page 14 of 24 theory of operation the ad8145 amplifiers use an architecture called active feedback, which differs from that of conventional op amps. the most obvious differentiating feature is the presence of two separate pairs of differential inputs compared to a conventional op amps single pair. typically, for the active feedback architecture, one of these input pairs is driven by a differential input signal while the other is used for the feedback. this active stage in the feedback path is where the term active feedback is derived. the ad8145 has an internal feedback resistor from each amplifier output to the negative input of its feedback input stage. this limits the possible closed-loop gain configurations for the ad8145. the active feedback architecture offers several advantages over a conventional op amp in several types of applications. among these are excellent common-mode rejection, wide input common- mode range, and a pair of inputs that are high impedance and completely balanced in a typical application. in addition, while an external feedback network establishes the gain response as in a conventional op amp, its separate path makes it entirely independent of the signal input. this eliminates any interaction between the feedback and input circuits, which traditionally causes problems with cmrr in conventional differential-input op amp circuits. another advantage of active feedback is the ability to change the polarity of the gain merely by switching the differential inputs. a high input impedance inverting amplifier can therefore be made. besides high input impedance, a unity-gain inverter with the ad8145 has a noise gain of unity, producing lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity-gain inverter. the two differential input stages of the ad8145 are each transconductance stages that are well matched. these stages convert the respective differential input voltages to internal currents. the currents are then summed and converted to a voltage, which is buffered to drive the output. the compensation capacitor is included in the summing circuit. when the feedback path is closed around the part, the output drives the feedback input to the voltage that causes the internal currents to sum to zero. this occurs when the two differential inputs are equal and opposite; that is, their algebraic sum is zero. in a closed-loop application, a conventional op amp has its differential input voltage driven to near zero under non- transient conditions. the ad8145 generally has differential input voltages at each of its input pairs, even under equilibrium conditions. as a practical consideration, it is necessary to limit the differential input voltage internally with a clamp circuit. therefore, the input dynamic ranges are limited to approximately 2.5 v (see the specifications section for more details). for this reason, it is not recommended to reverse the input and feedback stages of the ad8145, even though some normal functionality may be observed under some conditions.
ad8145 rev. a | page 15 of 24 applications information overview the ad8145 contains three independent active feedback amplifiers that can be effectively applied as differential line receivers for red-green-blue (rgb) signals or component video signals, such as ypbpr, transmitted over utp cable. the ad8145 also contains two general-purpose comparators with hysteresis that can be used to receive digital signals or to extract video synchronization pulses from received common-mode signals that contain encoded synchronization signals. the comparators, which receive power from the positive supply, are referenced to gnd and require greater than 4.5 v on the positive supply for proper operation. if the comparators are not used, then a split 2.5 v can be used with the amplifiers operating normally. the ad8145 includes a power-down feature that can be asserted to reduce the supply current when a particular device is not in use. basic closed-loop gain configurations each amplifier in the ad8145 comprises two transconductance amplifiersone for the input signal and one for negative feedback. note that the closed-loop gain of the amplifier used in the signal path is defined as the single-ended output voltage of the amplifier divided by its differential input voltage. therefore, each amplifier in the ad8145 provides differential-to-single-ended gain. additionally, the amplifier used for feedback has two high impedance inputsthe feedback input, where the negative feedback is applied, and the ref input, that can be used as an independent single-ended input to apply a dc offset to the output signal. the ad8145 contains on-chip feedback networks between each amplifier output and its respective feedback input. the closed- loop gain of the amplifier is set to 1 by connecting the amplifier output directly to its respective gain_x pin. doing this places the on-chip resistors and capacitor in parallel across the amplifier output and feedback pin. the small feedback capacitor mitigates the effects of the summing-node capacitance, which is most problematic in the unity gain case. closed-loop gain of an amplifier is set to 2 by connecting the respective gain_x pin to a reference voltage, often directly to ground. in figure 1 , r = 350 and c = 2 pf. some basic gain configurations implemented with an ad8145 amplifier are shown in figure 33 through figure 36 . gain ref r r 0.01f 0.01f +5 v ?5v c out v ou t v in v ref 06307-034 figure 33. basic gain = 1 circuit: v out = v in + v ref the gain equation for the circuit in figure 33 is v out = v in + v ref (1) in this configuration, the voltage applied to the ref pin appears at the output with a gain of 1. figure 34 illustrates one way to operate an ad8145 amplifier with a gain of 2. gain ref r r 0.01f 0.01f +5 v ?5v c v ref v out v in 06307-035 figure 34. basic gain = 2 circuit: v out = 2(v in + v ref ) the gain equation for the circuit in figure 34 is v out = 2( v in + v ref ) (2)
ad8145 rev. a | page 16 of 24 to achieve unity gain from v ref to v out in this configuration, divide v ref by the same factor used in the feedback loop; the divider resistors, r d , need not be the same values used in the internal feedback loop. figure 35 illustrates this approach. gain ref r r 0.01f 0.01f +5 v ?5v c v ref v out v in r d r d 06307-036 figure 35. basic gain circuit: v out = 2v in + v ref the gain equation for the circuit in figure 35 is v out = 2v in + v ref (3) another configuration that provides the same gain equation as equation 3 is shown in figure 36 . in this configuration, it is important to keep the source resistance of v ref much smaller than 350 to avoid gain errors. gain ref r r 0.01f 0.01f +5 v ?5v c v ref v out v in 06307-037 figure 36. basic gain circuit: v out = 2v in + v ref for stability reasons, the inductance of the trace connected to the ref_x pin must be kept to less than 10 nh. the typical inductance of 50 traces on the outer layers of the fr-4 boards is 7 nh/in, and on the inner layers, it is typically 9 nh/in. vias must be accounted for as well. the inductance of a typical via in a 0.062-inch board is 1.5 nh. if longer traces are required, a 200 resistor should be placed in series with the trace to reduce the q-factor of the inductance. in many dual-supply applications, v ref can be directly connected to ground right at the device. terminating the input one of the key benefits of the active feedback architecture is the separation that exists between the differential input signal and the feedback network. because of this separation, the differential input maintains its high cmrr and provides high differential and common-mode input impedances, making line termination a simple task. most applications that use the ad8145 involve transmitting broad- band video signals over 100 utp cables and use dc-coupled terminations. the two most common types of dc-coupled terminations are differential and common-mode. differential termination of 100 utp cables is implemented by simply connecting a 100 resistor across the amplifier input, as shown in figure 37 . gain ref r r 0.01f 0.01f +5 v ?5v c out v ou t v in 100 ? utp 100? 06307-038 figure 37. differential-mode termination with g = 1 some applications require common-mode terminations for common-mode currents generated at the transmitter. in these cases, the 100 termination resistor is split into two 50 resistors. the required common-mode termination voltage is applied at the tap between the two resistors. in many of these applications, the common-mode tap is connected to ground (v term (cm) = 0). this scheme is illustrated in figure 38 . gain ref r r 0.01f 0.01f +5 v ?5v c out v ou t v in 100 ? utp 50 ? 50 ? v term (cm) 06307-039 figure 38. common-mode termination with g = 1
ad8145 rev. a | page 17 of 24 input clamping a simple way to implement a clamp is to use a number of diodes in series. the resultant clamping voltage is then the sum of the clamping voltages of individual diodes. the differential input that is assigned to receive the input signal includes clamping diodes that limit the differential input swing to approximately 5.5 v p-p at 25c. because of this, the input and feedback stages should never be interchanged. a 1n4448 diode has a forward voltage of approximately 0.70 v to 0.75 v at typical current levels that are seen when it is being used as a clamp, and 2 pf maximum capacitance at 0 v bias. (the capacitance of a diode decreases as its reverse-bias voltage is increased.) the series connection of two 1n4448 diodes, therefore, has a clamping voltage of 1.4 v to 1.5 v. figure 40 shows how to limit the differential input voltage applied to an ad8145 amplifier to 1.4 v to 1.5 v (2.8 v p-p to 3.0 v p-p). note that the capacitance of the two series diodes is half that of one diode. different numbers of series diodes can be used to obtain different clamping voltages. the supply current drawn by the ad8145 has a strong dependence on the input signal magnitude because the input transconductance stages operate with differential input signals that can be up to a few volts peak-to-peak. this behavior is distinctly different from that of traditional op amps, where the differential input signal is driven to essentially 0 v by negative feedback. for most applications, including receiving rgb video signals, the input signal magnitudes encountered are well within the safe operating limits of the ad8145 over its full power supply and operating temperature ranges. in some extreme applications where large differential and/or common-mode voltages are encountered, external clamping may be necessary. external common-mode clamping is also sometimes required when an unpowered ad8145 receives a signal from an active driver. in this case, external diodes are required when the current drawn by the internal esd diodes cannot be kept to less than 5 ma. r t is the differential termination resistor, and the series resistances, r s , limit the current into the diodes. the series resistors should be highly matched in value to preserve high frequency cmrr. positive clamp negative clamp r s r t v in r s ? + gain ref r r 0.01f 0.01f +5 v ?5v c out v out 06307-041 figure 39 shows a general approach to external differential-mode clamping. positive clamp negative clamp r s r t v in r s ? + gain ref r r 0.01f 0.01f +5 v ?5v c out v out 06307-040 figure 40. using two 1n4448 diodes in series as a clamp many other nonlinear devices can be used as clamps. the best choice for a particular application depends upon the desired clamping voltage, response time, parasitic capacitance, and other factors. when using external differential-mode clamping, it is important to ensure that the series resistors (r s ), the sum of the parasitic capacitance of the clamping devices, and the input capacitance of the ad8145 are small enough to preserve the desired signal bandwidth. figure 39. differential-mo de clamping with g = 1 the positive and negative clamps are nonlinear devices that exhibit very low impedance when the voltage across them reaches a critical threshold (clamping voltage), thereby limiting the voltage across the ad8145 input. the positive clamp has a positive threshold, and the negative clamp has a negative threshold. a diode is a simple example of such a clamp. schottky diodes generally have lower clamping voltages than typical signal diodes. the clamping voltage should be larger than the largest expected signal amplitude, with enough margin to ensure that the received signal passes without being distorted.
ad8145 rev. a | page 18 of 24 figure 41 shows a specific example of external common-mode clamping. gain ref r r 0.01f 0.01f +5v ?5v c out v out v+ v + v? v? 3 2 1 3 2 1 v in + ? r t r s r s hbat-540c hbat-540c 06307-042 figure 41. external common-mode clamping the series resistances, r s , limit the current in each leg, and the schottky diodes limit the voltages on each input to approximately 0.3 v to 0.4 v over the positive power supply, v+, and to 0.3 v to 0.4 v below the negative power supply, v?. the required signal bandwidth, the line impedance, and the effective differential capacitance due to the ad8145 inputs and the diodes determine the maximum r s value. as with the differential clamp, the series resistors should be highly matched in value to preserve high frequency cmrr. pcb layout considerations the two most important issues with regard to pcb layout are minimizing parasitic signal trace reactances in the feedback network and providing sufficient thermal relief. excessive parasitic reactances in the feedback network cause excessive peaking in the frequency response of the amplifier and excessive overshoot in its step response due to a reduction in phase margin. oscillation occurs when these parasitic reactances are increased to a critical point where the phase margin is reduced to zero. minimizing these reactances is important to obtain optimal performance from the ad8145. general high speed layout practices should be adhered to when applying the ad8145. controlled impedance transmission lines are required for incoming and outgoing signals, referenced to a ground plane. typically, the input signals are received over 100 differential transmission lines. a 100 differential transmission line is readily realized on the pcb using two well-matched, closely-spaced, 50 single-ended traces that are coupled through the ground plane. the traces that carry the single-ended output signals are most often 75 for video signals. output signal connections should include series termination resistors that are matched to the impedance of the line they are driving. when driving high impedance loads over very short traces, impedance matching is not required. in these cases, small series resistors should be used to buffer the capacitance presented by the load. broadband power supply decoupling networks should be placed as close as possible to the supply pins. small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. minimizing parasitic feedback reactances parasitic trace capacitance and inductance are both reduced in the unity-gain configuration when the feedback trace that connects the out_x pin to the gain_x pin is reduced in length. removing the copper from the planes below the trace reduces trace capacitance, but increases trace inductance, because the loop area formed by the trace and ground plane is increased. a reasonable compromise that works well is to void all copper directly under the feedback trace and component pads with margins on each side approximately equal to one trace width. combining this technique with minimizing trace length is effective in keeping parasitic trace reactance in the unity-gain feedback loop to a minimum. maximizing heat removal a square array of thermal vias works well to connect the exposed paddle to internal ground planes. the vias should be placed inside the pcb pad that is soldered to the exposed paddle and should connect to all ground planes. the ad8145 includes ground connections on its corner pins. these pins can be used to provide additional heat removal from the ad8145 by connecting them between the pcb pad that is soldered to the exposed paddle and a ground plane on the component side of the board. this layout technique lowers the overall package thermal resistance. use of this technique is not required, but it does result in a lower junction temperature. designs must often conform to design for manufacturing (dfm) rules that stipulate how to lay out pcbs in such a way as to facilitate the manufacturing process. some of these rules require thermal relief on pads that connect to planes, and the rules may limit the extent to which this technique can be used.
ad8145 rev. a | page 19 of 24 driving a capacitive load the ad8145 typically drives either high impedance loads over short pcb traces, such as crosspoint switch inputs, or doubly terminated coaxial cables. a gain of 1 is commonly used in the high impedance case because a 6 db transmission line termination loss is not incurred. a gain of 2 is required when driving cables to compensate for the 6 db termination loss. in all cases, the output must drive the parasitic capacitance of the feedback loop, conservatively estimated to be 1 pf, in addition to the capacitance presented by the actual load. when driving a high impedance input, it is recommended that a small series resistor be used to buffer the input capacitance of the device being driven. clearly, the resistor value must be small enough to preserve the required bandwidth. in the ideal doubly terminated cable case, the ad8145 output sees a purely resistive load. in reality, there is some residual capacitance, which is buffered by the series termination resistor. figure 42 illustrates the high impedance case, and figure 43 illustrates the cable driving case. r s c in gain ref r r 0.01f 0.01f +5 v ?5v c out v in v ref 06307-043 figure 42. buffering the input capacitance of a high-z load with g = 1 gain ref r r 0.01f 0.01f +5 v ?5v c v ref v in r s c s r l out 06307-044 figure 43. driving a doubly terminated cable with g = 2 power-down the power-down feature can be used to reduce power consumption when a particular device is not in use and does not place the output in a high-z state when asserted. the power-down feature is asserted when the voltage applied to the power-down pin drops to approximately 2 v below the positive supply. the ad8145 is enabled by pulling the power-down pin to the positive supply. automotive products the ad8145w product is qualified per the aec-q100 for use in automotive applications. this model meets stringent automotive performance and quality requirements and offers the same functionalities as the commercial and industrial grade devices but operates over a temperature range of ?40c to +105c. for more information, contact your local analog devices, inc., sales representative. comparators in addition to general-purpose applications, the two on-chip comparators can be used to decode video sync pulses from the received common-mode voltages or to receive differential digital information. built-in hysteresis helps to eliminate false triggers from noise. the comparator outputs are designed to drive source-terminated transmission lines. the source termination technique uses a resistor in-series with each comparator output such that the sum of the comparator source resistance (20 ) and the series resistor equals the transmission line characteristic impedance. the load end of the transmission line is high impedance. when the signal is launched into the source termination, its initial value is one- half of its source value because its amplitude is divided-by-2 by the voltage divider formed by the source termination and the transmission line. at the load, the signal experiences nearly 100% positive reflection due to the high impedance load and is restored to nearly its full value. this technique is commonly used in pcb layouts that involve high speed digital logic. an internal linear voltage regulator derives power for the comparators from the positive supply; therefore, the ad8145 must always have a minimum positive supply voltage of 4.5 v.
ad8145 rev. a | page 20 of 24 sync pulse extraction using comparators the ad8134 encoding equations are given in equation 4, equation 5, and equation 6. the ad8145 is particularly useful in kvm applications. kvm networks transmit and receive computer video signals that typically comprise red, green, and blue (rgb) video signals and separate horizontal and vertical sync signals. because the sync signals are separate and not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common-mode voltages of the rgb signals. the ad8134 triple differential driver is a natural complement to the ad8145 and performs the sync pulse encoding with the necessary circuitry on-chip. [ ] hv k vred cm ?= 2 (4) [ ] v2 2 ?= k vgreen cm (5) [ ] hv k vblue cm += 2 (6) where: red v cm , green v cm , and blue v cm are the transmitted common- mode voltages of the respective color signals. k is an adjustable gain constant that is set by the ad8134. v and h are the vertical and horizontal sync pulses, defined with a weight of ?1 when the pulses are in their low states and a weight of +1 when they are in their high states. the ad8134 data sheet contains further details regarding the encoding scheme. figure 44 illustrates how the ad8145 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the rgb common-mode voltages by the ad8134 . received red video hsync red cmv green cmv blue cmv 50 ? 50 ? 1k? 1k? vsync received green video 50 ? 50 ? received blue video 50 ? 50 ? r s r s 475 ? 47pf 47pf 06307-045 figure 44. extracting sync signals from received common-mode signal
ad8145 rev. a | page 21 of 24 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) 112408-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 45. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad8145ycpz-r2 ?40c to +105c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 ad8145ycpz-rl ?40c to +105c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 ad8145ycpz-r7 ?40c to +105c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 AD8145WYCPZ-R7 2 ?40c to +105c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 1 z = rohs compliant part. 2 w = automotive qu alified product.
ad8145 rev. a | page 22 of 24 notes
ad8145 rev. a | page 23 of 24 notes
ad8145 rev. a | page 24 of 24 notes ?2006C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06307-0-1/10(a)

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